As integrated circuit fabrication advances from very large scale integration (VLSI) to ultra-large scale integration (ULSI), semiconductor manufacturers continue to develop techniques to construct integrated circuits with structures having dimensions in the sub-micron range on a semiconductor substrate. Improvements in photolithographic processing techniques that can be employed to produce integrated circuits comprising several million transistors per die have substantially contributed to the miniaturization of active semiconductor devices to dimensions below a single micron. The fabrication of these semiconductor devices typically involves the transfer of circuit image patterns from a photolithographic reticle onto a photoresist layer covering a wafer of semiconductor material using an imaging lens apparatus. The reticle is often itself constructed from a substrate of silicon dioxide and is typically patterned with areas of differing transmissivity thereon, some of these areas being opaque and others being substantially transparent. Collectively, the patterned areas of the reticle represent either the positive or negative images of an integrated circuit structure depending on whether a negative or positive photoresist is utilized. After being properly positioned and aligned over the semiconductor wafer, the reticle is then subjected to electromagnetic radiation, typically in the ultra-violet region of the spectrum. The electromagnetic radiation passes through transparent portions of the reticle, striking portions of the photoresist layer on the wafer. The resist coating is then developed and etched so as to impart a positive or negative image of the reticle pattern onto the photoresist layer remaining on the wafer.
Conventional photolithographic methods of fabricating integrated circuits on a substrate typically involve stepping a reticle and imaging apparatus across a photoresist coated wafer and then repeatedly transferring the reticle image pattern to adjacent areas on the wafer. Each of the individual areas on the wafer containing the circuitry image is termed a die. Typically the wafer is cut or otherwise segmented at the end of the fabrication process so that the dies are separated from one another for subsequent packaging as individual integrated circuit chips. The region of the reticle bearing the circuity image pattern is commonly referred to as a reticle field, and the corresponding patterned region on each die is usually termed the substrate field, or chip field. Depending on the size of the substrate and individual die, a substrate may contain either a few dice or several dozen repetitions of the individual die pattern. The dice are usually arranged uniformly across the substrate in rows and columns. A wafer may undergo several imaging or photolithographic steps, depending on the complexity of the integrated circuit to be formed, with different reticles being employed at different times during the fabrication process to produce individual patterned layers on the die that collectively form the composite integrated circuit structure. This process is generally regarded as being well suited for fabricating integrated circuits having repeating structures such as DRAMs (Dynamic Random Access Memories) and SRAMs (Static Random Access Memories).
As integrated circuits become increasingly complex, however, the integrated circuit structures within an individual die have become significantly smaller and more dense. Larger reticles are often required to transfer larger and more complex circuit images to substrate fields of increased dimensions. Because of inherent image resolution limitations associated with conventional photolithographic processes, imaging and alignment errors are often introduced when fine line structures having sub-micron dimensions are produced on relatively large reticles. Current photolithographic imaging tools, as a consequence, are currently capable of patterning a field with a maximum surface area of only approximately 4.0 cm.sup.2 if fine line structures with dimensions in the sub-micron range are included on the reticle.
The inherent limitations associated with producing relatively large reticles having structures with sub-micron dimensions have motivated integrated circuit manufactures to develop new methods of fabricating reticles with larger fields. One such method, known as "reticle stitching," is directed to producing larger reticle fields by sub-dividing the circuitry pattern, typically into four smaller subfields of equal dimension, and then stitching, that is, recomposing the subfield patterns together on a second reticle to form a large composite reticle field thereon. As illustrated in FIG. 1 of the drawings, a reticle 8 having a field 10 is shown as a composite field fabricated using a conventional stitching technique. Generally, reticle field 10 is a representation of the image patterns of an integrated circuit structure. The reticle 8 is constructed by first photolithographically patterning on separate reticles smaller subfields 12, 14, 16, and 18, with each subfield bearing a portion of the image pattern of the integrated circuit structure, and then stitching the subfields together along stitching boundaries 20, 22, 24, and 26 to form the composite reticle field 10. As discussed in U.S. Pat. No. 5,055,383, issued to Koblinger et al. (hereinafter referred to as "Koblinger"), the image patterns of subfields 12, 14, 16, and 18 of FIG. 1 that are transferred to reticle 8 must adjoin each other with a very high accuracy in order to avoid any alignment errors that otherwise occur with respect to the millions of fine line interconnections necessary to "re-connect" adjacent subfields along the stitching boundaries 20, 22, 24, and 26.
The manufacture of composite reticles formed by stitching together the interconnections between subfields in accordance with conventional techniques is generally regarded as a problematic process that currently provides unacceptably low yields. Further, because the fabrication of the reticle, or, more accurately, sets of reticles which together define a three dimensional integrated circuit structure, constitutes the primary expenditure with regard to the fabrication of integrated circuits, low reticle yields represent a significant loss of investment. There continues to exist in the integrated circuit manufacturing community a need to accommodate highly complex circuitry image patterns of powerful integrated circuits, and to overcome the inherent field size limitations associated with current photolithographic techniques. The present invention fulfills these needs.